The invention relates to a voltage conversion circuit, and more particularly, to a voltage conversion circuit including a charge pump circuit for boosting an input voltage.
There is a practice in the prior art that whenever a semiconductor memory, such as a DRAM, is not in use, an external supply voltage which has a lower than normal level is provided to the semiconductor memory, thus switching the voltage supply to a low voltage mode. In the low voltage mode, an external supply voltage of a level which is sufficient to enable a refresh operation for maintaining stored information is used, thus reducing the power dissipation of the semiconductor memory.
A semiconductor memory is generally provided with a voltage conversion circuit which boosts an external supply voltage to supply various internal circuits with a boosted voltage or voltages. For example, such a voltage conversion circuit boosts an external supply voltage of 3.3 volts, which is supplied during a normal voltage mode, to a voltage range from 4.5 to 4.8 volts or boosts an external supply voltage of 2.0 volts, which is supplied during a low voltage mode, to a voltage range from 3.5 to 3.8 volts.
A conventional charge pump circuit 100 as shown in FIG. 1 is extensively employed as a voltage conversion circuit.
Referring to FIG. 1, the charge pump circuit 100 comprises first and second booster stages 1, 2, first and second inverter circuits 3, 4, first, second and third gate transistors T1, T2, T3 and a stabilizing capacitive element C0. The first booster stage 1 is connected to an external supply voltage Vcc via the first gate transistor T1 which is formed by an NMOS transistor. The second transistor T2 which is formed by a PMOS transistor is connected between the first booster stage 1 and the second booster stage 2. The second booster stage 2 is connected to an internal bus which supplies a voltage Vout to various circuits via the third gate transistor T3 formed by a PMOS transistor.
The first booster stage 1 comprises a first capacitive element C1 which has a first terminal connected to the source terminals of the first and second gate transistors T1, T2 and a second terminal connected to the output terminal of the first inverter circuit 3 which is formed by a CMOS transistor. The second booster stage 2 comprises a second capacitive element C2 which has a first terminal connected to the drain terminal of the second gate transistor T2 and to the source terminal of the third gate transistor T3 and which also has a second terminal connected to the output terminal of the second inverter circuit 4 which is formed by a CMOS transistor. The stabilizing capacitive element C0 has a first terminal connected to the internal bus and a second terminal connected to ground, but which may alternatively be connected to the external supply voltage Vcc.
When the first inverter circuit 3 delivers an L level (0 volt) signal, the first capacitive element C1 is charged in response to the turn-on of the first gate transistor T1 and the turn-off of the second gate transistor T2. The potential at the first terminal of the capacitive element C1 then rises to the external supply voltage Vcc.
Subsequently when the first inverter circuit 3 delivers an H level (positive xcex1 volt) signal when the first gate transistor T1 is off, the potential at the first terminal of the first capacitive element C1 rises to a primary boosted voltage V1 which is equal to Vcc+xcex1, where xe2x80x9cxcex1xe2x80x9d represents the external supply voltage Vcc. Thus, the first inverter circuit 3 operates on the external supply voltage Vcc, which is then supplied as an H level signal to the first capacitive element C1.
When the second inverter circuit 4 delivers an L level signal when the third gate transistor T3 is off, the second capacitive element C2 is charged in response to the turn-on of the second gate transistor T2, and the potential at the first terminal of the capacitive element C2 rises to the primary boosted voltage V1 which is equal to Vcc+xcex1.
Subsequently, when the second inverter circuit 4 delivers an H level (positive xcex1) signal when the second gate transistor T2 is off, the potential at the first terminal of the second capacitive element C2 rises to a secondary boosted voltage V2 which has the predetermined voltage xcex1 added to the primary boosted voltage or V1+xcex1=Vcc+2xcex1. The second inverter circuit 4 also operates on the external supply voltage Vcc, which is then supplied as an H level signal to the second capacitive element C2.
Subsequently, when the third gate transistor T3 is turned on, the secondary boosted voltage V2 which has charged the second capacitive element C2 is supplied to various internal circuits as an internal bus voltage Vout. Thus, the charge pump circuit 100 produces the internal bus voltage Vout by boosting the external supply voltage Vcc by 2xcex1. By repeating the described boosting operation, the charge is stored across the stabilizing capacitive element C0 to raise the potential of the internal bus voltage source Vout.
It is to be noted, however, that the external supply voltage Vcc supplied to the charge pump circuit 100 has different levels between the normal voltage mode and the low voltage mode. The charge pump circuit 100 has a boosting efficiency which changes greatly with a variation in the external supply voltage Vcc. The lower the external supply voltage Vcc, the more rapidly the booster efficiency is degraded. Circuit parameters (capacitances of the first and second capacitive elements C1, C2) of the charge pump circuit 100 are chosen on the basis of the low voltage mode so that no difficulty is caused by an insufficient booster efficiency which prevails in the low voltage mode.
However, when the circuit parameters of the charge pump circuit 100 are chosen on the basis of the low voltage mode, an excessive booster capability results when the external supply voltage is high as in the normal voltage mode which is assumed during a read/write operation, causing an undesirable increase in the power dissipation.
To reduce the power dissipation in the normal voltage mode, the second and third gate transistors T2, T3 are turned on simultaneously after the first booster stage 1 has produced the primary boosted voltage V1, thus effecting a single stage booster pumping, which means delivering the primary boosted voltage V1 as the internal bus voltage Vout, rather than boosting the primary boosted voltage in the second booster stage 2 while maintaining an output from the second inverter circuit 4 at its L level. In contrast to the single stage booster pumping, the term xe2x80x9ctwo stage booster pumpingxe2x80x9d refers to combining the booster operations in both the first and second booster stages 1, 2 to deliver the secondary boosted voltage V2 as the internal bus voltage Vout.
In the single stage booster pumping, the primary boosted voltage V1 produced by the first booster stage 1 is delivered as the internal bus voltage Vout via the second and third gate transistors T2, T3. Thus, a flow of the charge via the second and third gate transistors T2, T3 produces a voltage drop or a current drop therein, resulting in a decrease in the booster efficiency. More specifically, the second and third gate transistors T2, T3 are formed by PMOS transistors, which do not produce a voltage drop across their sources and drains in a d.c. operation. However, because the transistors T2, T3 are connected in series, they exhibit an increased effective channel length. This prevents the charge discharged from the first capacitive element C1 in an a.c. operation from being delivered in its entirety from the third gate transistor T3, causing a voltage drop or a reduction in the booster efficiency. The booster efficiency of the charge pump circuit 100 is also degraded by an unnecessary charging of the second capacitive element C2. The same is true in the case of an alternate form of single stage booster pumping in which the first booster stage 1 remains quiescent while the second booster stage 2 operates as a charge pump.
In addition, it is essential that the circuit parameters of the charge pump circuit 100 be predetermined increased values in order to enhance the boost capability. However, an increase in the capacitance of the first and second capacitive elements lead to an increase in the chip area and a consequent increase in the size of the semiconductor device and its cost.
On the other hand, the charge pump circuit of the type described requires a determination of optimal circuit parameters. Optimal circuit parameters as well as a timing to switch from the low to the normal voltage mode or vise-versa are determined from previous accurate measurements of various responses of the boosted voltages during each of the single stage and the two stage booster pumping control. This requires that tests be conducted to determine the response of the internal bus voltage Vout with respect to the external supply voltage Vcc during both the two stage and the single stage booster pumping operation.
It is an object of the present invention to provide a voltage conversion circuit which performs an efficient booster operation in accordance with the level of an external supply voltage.
It is another objective of the present invention to provide a voltage conversion circuit which facilitates the determination of optimal circuit parameters.
To achieve the above objective, the present invention provides a charge pump circuit comprising: a plurality of voltage conversion stages connected between an input supply and a supply output; a plurality of gate transistors, each connected between respective voltage conversion stages, between a first stage of said voltage conversion stages and the input supply, or between last stage of said voltage conversion stages and the supply output; and bypass transistor connected between one of the input supply and the supply output and one of said voltage conversion stages, the bypass transistor connected in parallel with at least one of said gate transistors.
The present invention further provides a charge pump circuit comprising: a pair of charge pumps connected in parallel to each other between an input supply and a supply output, wherein each charge pump includes: a plurality of voltage conversion stages connected between the input supply and the supply output, a plurality of gate transistors, each connected between respective voltage conversion stages, between a first stage of said the voltage conversion stages and the input supply, or between last stage of said voltage conversion stages and the supply output; and a bypass transistor connected between one of the input supply and the supply output and one of said voltage conversion stages, the bypass transistor connected in parallel with at least one of said gate transistors.
The present invention provides a method of driving a charge pump circuit having a plurality of voltage conversion stages connected between an input supply and a supply output, a plurality of gate transistors, each connected between respective voltage conversion stages, between a first stage of said voltage conversion stages and the input supply, or between last stage of said voltage conversion stages and the supply output, and a bypass transistor connected between one of the input supply and the supply output and one of the voltage conversion stages, the bypass transistor connected in parallel with at least one of said gate transistors, the method comprising the steps of: operating all of the voltage conversion stages and the gate transistors in a predetermined sequence while maintaining the one or more bypass transistors off to cause all of the voltage conversion stages to convert the voltage of the input supply to a first voltage for the supply output; and operating at least one of the voltage conversion stages, at least one of the gate transistors and at least one of the bypass transistors in a predetermined sequence to cause at least one of the voltage conversion stages to convert the voltage of the input supply to a second voltage for the supply output.
The present invention further provides a voltage conversion circuit comprising: a charge pump circuit including a plurality of voltage conversion stages connected between an input supply and a supply output, a plurality of gate transistors, each connected between respective voltage conversion stages, between a first stage of said voltage conversion stages and the input supply, or between last stage of said voltage conversion stages and the supply output, and a bypass transistor connected between one of the input supply and the supply output and one of said voltage conversion stages, the bypass transistor connected in parallel with at least one of said gate transistors; a drive circuit connected to the plurality of voltage conversion stages, the plurality of gate transistors and the one or more bypass transistors for controlling the plurality of voltage conversion stages, the plurality of gate transistors, and the one or more bypass transistors; and a mode switching circuit connected to the drive circuit for providing a mode signal to the drive circuit.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.